Generally, as semiconductor memory devices become more integrated and smaller, the degradation rate of the wiring for on-chip conductive lines becomes markedly greater as the pitch between wires become narrower. In addition, manufacturing yield decreases with increasing integration of a memory device and an inner defect rate increases as chips become larger in size.
Integrated read-write semiconductor memory devices employing field effect transistors for most or all main memory cell elements, require that a test operation be carried out during the fabrication process to verify memory performance. Excessively high test costs of high density memory chips is capable of influencing the fabrication process. Test costs are usually a large portion of total manufacturing costs. Such test costs include charges for using a testing apparatus as well as other depreciation and incidental costs. A large portion of total costs are associated with the use of a test apparatus, and the remaining portion is the result of depreciation and incidental costs.
As test time for an integrated memory device becomes unavoidably long, a memory circuit's density should be reduced to at least improve reliability in fabrication. Reduced density leads not only to reduced test time but also to reduced dependence on determinations of product reliability on test results.
Reducing test costs in the manufacturing of memory devices is an ongoing effort. A parallel test with a multi-bit data scheme has recently been proposed. Such a scheme, however, is problematic because it requires an expensive test apparatus operating at high speeds. This scheme is also subject to high incidental costs.
Different additional schemes have further been proposed such as those disclosed in a Technical Research Report published by Japanese Institute of Electronics, Information and communication SDM 89-31, 32(filed on Jun. 21, 1989) and in SDM 90-199 (filed on Mar. 27, 1991), both discussing a line mode test (LMT) scheme and a self test (ST) scheme.
In the SDM 89-31 paper ("A memory array architecture adaptable for a 16-Mb DRAM"; hereinafter referred to as "Ref.1"), shown in FIG. 1, the disclosed circuit is provided with a comparator circuit 1 and a multi-purpose register 2 functioning in LMT mode to parallel test the memory chip. This circuit reduces test time over earlier test circuits. The LMT tests all memory cells connected to a batch-writing signal thus increasing the number of data bits that can be tested. By employing multi-purpose register 2 as a data register and as a data-of-reckoned value register (which `data-of-reckoned value` is the expected value of readout data), a random pattern test is possible and a sufficient reduction in test time is realized.
In the SDM 89-32 paper ("A 55-ns 16-Mb DRAM using a self test scheme"; hereinafter referred to as "Ref. 2"), a circuit is disclosed which shortens test time by packaging data bits into parts or into a net. The techniques disclosed are aimed at reducing costs during testing operations.
The disclosed way to reduce test time is by simplifying or streamlining the test operation. For example, a BIST (built in self test) scheme automatically initiates a test function in response to a test enable clock applied externally from the chip. Thus chips can be randomly tested. A memory board having memory chips embedded thereon and tested with a BIST circuit may have a short test time. Consequently, test costs are reduced and the partial function of an LSI tester is substituted by the BIST circuit.
The specific circuit architecture of this Ref. 2 is shown in FIG. 2. This circuit includes ROM 21 for storing the sequential program steps for a test operation, program counter 22 for controlling ROM 21, address counter 23 for generating test addresses, data generator 24 generating test data, data comparator 25 for comparing the test data with data read from memory cells, and test clock generator 26 for providing a first signal to control the timing of each circuit and a second signal to control the main memory body during self test operation.
The operation of the self test circuit of FIG. 2 and the respective functions of circuit elements will be described in connection with a description of a matching test mode. A matching test is accomplished by the program operation of twelve steps, each step corresponding to a step in the test cycle. The steps consist of:
a primary step for initializing the test circuit, corresponding to clear cycle;
a first step for writing data of logic level "0" as background data into all memory cells;
second and third steps comparing `reckoned write data` logic level "0", which might be written with data retrieved from a respective memory cell and writing data "1" thereto instead--repeating steps two and three for each bit counting up from the first bit to the Nth bit;
a fourth and fifth steps for performing the second and third steps on the basis of complementary data;
a sixth to tenth steps for repeating steps two through five for each bit counting down from the Nth bit to the first bit; and
an eleventh step for generating a flag to terminate the test operation.
In this test operation, although an error is detected during the sequential processing of the above steps, the sequence goes to termination without pause, with the exception that an error condition acknowledgement is made to the outside.
Referring to the SDM 90-199 paper ("A 64-Mb DRAM in the scheme of merged match-line test"; hereinafter referred to as "Ref. 3") to be discussed in connection with FIG. 3A, this paper discloses test times as a function of the various types of DRAM devices. As illustrated, bit-by-bit test accessing can exhaust ten seconds of test time in which time every cell data in a 64-Mb DRAM would have been read out. A shipping test of several ten items requires more than one hour to completely perform a test operation thereof--a shipping test being necessary to check an IC before it is shipped.
A multi-bit test scheme (MBT), performing four bit testing in a 1-Mb DRAM, has also been proposed. The MBT scheme, however, is not suited for 4-to 64-Mb DRAMs. The sufficient reduction in test time of an MBT test may not be achieved as the size of test data cannot override as many as those for 16 to 64 bits. Additionally, such a scheme requires several thousand pre-amplifiers in order to parallel test several kilo bits, a clear limitation when reducing chip size is a critical design factor.
Because of problems in other proposed schemes, the LMT scheme operating on a batch-testing basis of all bits on each word line has been most successful in efforts sharply to reduce test time in high density DRAMS. The LMT scheme, however, requires exclusive match lines (wires) for transferring reference data, as well as comparators associated with corresponding pairs of bit lines.
In the MMT scheme disclosed in Ref. 3, data output lines used under normal write mode are functionally converted to serve as match lines. Similarly, the portion of the chip operating as a differential amplifier in normal read mode operates as a wired-OR circuit. Consequently, test circuit chip area is not greater than 0.1 percent of total chip area. A comparison between the conventional LMT and MMT schemes is shown in FIG. 3B. The MMT scheme, much like the LMT scheme, performs a test operation for several kilo bits of batch data at a time. Read-out time for a 64-Mb DRAM is completed in 614 .mu.s, with a cycle time of 150 ns (refer to FIG. 3A).
The speed-up of access time during actual use together with reduction in test time are essential factors in DRAM test circuit design. To achieve greater speed-up of access time in an MMT scheme, the chip architecture is provided with data output and input lines such that data read out from selected memory cells are amplified using sense amplifiers as well as differential amplifiers to achieve an access time of 45 ns.
Despite good performance characteristics of an MMT, potential for improvement of this test circuit was always thought possible.
Thin transistor technology wherein transistor channels are formed using a polycrystalline or amorphous silicon layer has been employed in liquid crystal devices and SRAM (static random access memory) devices.
Because circuit elements are fabricated on a semiconductor substrate, the addition of elements necessarily causes chip size to increase. Hence, when a unit cost for fabricating a chip is high as to increase the overall product cost despite low costs of a testing apparatus, it is impossible to reduce overall test and product costs.